(i) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more specifically, to an improvement in step of patterning a conductive layer over an uneven surface to thereby form a gate electrode.
(ii) Description of the Related Art
In a process of manufacturing a semiconductor device, a selective etching, a local oxidation or the like causes various steps to be formed on a semiconductor substrate. The surface of the substrate is thereby made uneven. It is required in a process of a device to perform a patterning of a conductive layer such as a polysilicon layer to form a wiring layer and/or a gate electrode. If such patterning is performed on a conductive layer deposited over the uneven surface, the patterned layer for a wiring layer or a gate layer is partially made narrow at the steps of the uneven surface, or is differentiated in size between upper and lower portions thereof.
Referring now to FIG. 3 and further to FIG. 4 which is a cross sectional view taken along line C-C' of FIG. 3, a field insulating layer 14 is selectively formed in the surface portion of a semiconductor substrate 11 to define an element formation area. Since the layer 14 is formed by selectively oxidizing the substrate 11, there is formed a step at the edge of the film 14. The element formation area is covered by a gate insulating film 15. In order to form a gate electrode, a polycrystalline silicon layer 16 is formed and further a photoresist layer 18 is formed.
As is apparent from FIG. 4, the resist layer 18 is varied in thickness at the step. That is, the resist film thickness of the step upper portion is different from that of the lower portion. For this reason due to a standing-wave effect in the photolithography step, the actual pattern of the polycrystalline silicon layer 16 is narrowed in the step of the oxide layer 14, as shown in FIG. 3. The gate electrode, which is made of the layer 16 by selective etching using the photoresist 18 as a mask, is thus also made narrow at the step. A transistor having the gate electrode thus formed easily suffers from a punch-through phenomenon at the narrow portion of the gate electrode due to the so-called short channel effect.
One of means for solving the the above problem is disclosed in U.S. Pat. No. 5,346,587. The method tight by this patent is explained below with reference to FIG. 5.
As shown in FIG. 5A, a field insulating layer 14 is selectively formed on a silicon substrate 11 to define an element isolation area A and an element formation area B. A polycrystalline silicon layer 16 is then deposited with 300 nm in thickness over the entire surface. Before that, a gate insulating film 15 is formed to cover the area B of the semiconductor substrate 11. Due to the formation of the layer 14, there is a step on the boundary portion between the element area B and the element separation area A. The step is about 100 nm. The surface of the polysilicon layer 16 is thereby made uneven.
Thereafter, a chemical mechanical polishing (CMP) is performed on the layer 16 to remove the step and make the surface thereof even, as shown in FIG. 5B. The photolithograph process is then performed to selectively etch the the polysilicon layer 16 to form a gate electrode. At this time, the surface of the polycrystalline silicon 16 is even, and the gate electrode is not substantially made narrow at the step.
However, according to this method, the polycrystalline silicon layer 16 to be the gate electrode is directly polished by the CMP. On the other hand, the amount of the polysilicon layer which has disappeared by the CMP changes considerably in accordance with the position of the wafer. For this reason, the film thickness of the polycrystalline silicon does not have a uniformity on the wafer surface. The dispersion is up to about 30 nm within the range on the surface.
In an nMOSFET, for example, when an arsenic is doped into the gate, the arsenic is not diffused all over the gate electrode at a thicker portion of the gate electrode, and thus the gate electrode is depleted. Conversely, in a pMOSFET, for example, a boron is protruded from the gate insulating film at a thinner portion of the gate electrode, and thus the boron is doped into a channel area. Due to this depletion of the gate electrode and protrusion of an impurity, when the film thickness dispersion of the gate electrode is present on the wafer surface, transistor characteristics are dispersed on the wafer surface.